1. Field of the Invention
The present invention relates to a signal transmission and reception circuit to be used for high speed digital transmission using a bus etc. inside a computer and specifically it relates to an apparatus and a method of adjusting the clock of a reception apparatus.
2. Description of the Related Art
A conventional transmission method of synchronizing clock signals between a transmission apparatus and a reception apparatus includes mainly following two methods which are performed in a signal transmission and reception processing between the processor LSI (Large Scale Integration) circuit and the chip set LSI circuit of a computer.
(a) Synchronous system
As shown in FIG. 1A, clock signals are respectively distributed to a transmission apparatus 102 and a reception apparatus 103 as a strobe signal from a clock driver (CLK driver) 101 and data signals are transferred between these apparatuses.
(b) Source Synchronous system
As shown in FIG. 1B, a clock signal is transmitted at the same time a data signal is transmitted to the reception apparatus 105 from the transmission apparatus 104 and then the reception apparatus 105 receives data using the clock signal.
In addition, a phase frequency comparison circuit and a signal processing circuit for delaying a clock signal are well-known (for example, refer to patent literatures 1 and 2).    [Patent literature 1] Japanese laid-open patent application publication No. 2002-135093    [Patent literature 2] Japanese laid-open patent application publication No. 05-258476
However, there is the following problem in the above-mentioned conventional transmission systems.
In the synchronous system (a), the clock signal and data signal are relatively lagged by both the piece-to-piece variations and a temperature/voltage fluctuation so that this system is not available for high speed transmission.
In the source synchronous system (b), the tolerance to the piece-to-piece variations and a temperature/voltage fluctuation are improved, but the time lag between a clock signal and a data signal becomes a problem when they are used in ultrahigh speed transmission. Furthermore, in the case of the data signal of a plurality of bits, a design for generating equal time lags between bits becomes required since the variation in wiring lengths among bits, etc. at the time of drawing a design influences these data signals.